View LTC3836_7324125.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3836 1 3836fa features applications description dual 2-phase, no r sense tm low v in synchronous controller the ltc ? 3836 is a 2-phase dual output synchronous step-down switching regulator controller with tracking that drives external n-channel power mosfets using few external components. the constant-frequency current mode architecture with mosfet v ds sensing eliminates the need for sense resistors and improves ef? ciency. the power loss and noise due to the esr of the input capacitance are minimized by operating the two control- lers out-of-phase. pulse-skipping operation provides high ef? ciency at light loads. the 97% duty cycle capability provides low dropout operation, extending operating time in battery-powered systems. the operating frequency is selectable from 300khz to 750khz, allowing the use of small surface mount induc- tors and capacitors. for noise sensitive applications, the LTC3836 operating frequency can be externally synchro- nized from 250khz to 850khz. the LTC3836 features an internal 1ms soft-start that can be extended with an external capacitor. a tracking input al- lows the second output to track the ? rst during start-up. the LTC3836 is available in the tiny thermally enhanced (4mm 5mm) qfn and 28-lead narrow ssop packages. high ef? ciency, 2-phase, dual synchronous dc/dc step-down converter n no current sense resistors required n out-of-phase controllers reduce required input capacitance n all n-channel synchronous drive n v in range: 2.75v to 4.5v n constant-frequency current mode operation n 0.6v 1.5% voltage reference n low dropout operation: 97% duty cycle n true pll for frequency locking or adjustment n selectable pulse-skipping/continuous operation n tracking function n internal soft-start circuitry n power good output voltage monitor n output overvoltage protection n micropower shutdown: i q = 6.5a n tiny low pro? le (4mm 5mm) qfn and narrow ssop packages n general purpose 3.3v to 1.x supplies n single lithium-ion powered devices n distributed dc power systems sense1 + v in LTC3836 sgnd sense2 + boost1 boost2 tg1 tg2 sw1 sw2 bg1 bg2 pgnd v fb1 v fb2 820pf v out1 1.8v at 15a v out2 1.2v at 15a 100 f 2 100 f 2 15k 820pf 15k 59k 59k 118k 59k 0.47 h 0.47 h i th1 3836 ta01 i th2 22 f 3 v in 3.3v ef? ciency/power loss vs load current load current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 60 40 100 1000 100000 10000 3836 ta01b 0 10000 10 100 1000 1 10 3.3v-1.2v power loss circuit of figure 15 3.3v-1.2v efficiency 3.3v-1.8v efficiency 3.3v-1.8v power loss typical application l , lt, ltc and ltm are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5929620, 6144194, 6304066, 6498466, 6580258, 6611131.
LTC3836 2 3836fa absolute maximum ratings boost1, boost2 voltages ....................... ?0.3v to 10v input supply voltage (v in ) ........................ ?0.3v to 4.5v plllpf, run/ss, sync/fcb, sense1 + , sense2 + , iprg1, iprg2 voltages ..................?0.3v to (v in + 0.3v) v fb1 , v fb2 , i th1 , i th2 , track/ss2 voltages ................................ ?0.3v to 2.4v (note 1) parameter conditions min typ max units main control loops input dc supply current normal mode shutdown uvlo (note 4) run/ss = v in run/ss = 0v v in = uvlo threshold ?200mv 450 6.5 4 700 15 10 a a a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise speci? ed. sw1, sw2 voltages ............................... ?2v to v in + 1v pgood ....................................................... ?0.3v to 10v operating temperature range (note 2).... ?40c to 85c storage temperature range ................... ?65c to 125c junction temperature (note 3) ............................. 125c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sw1 n/c iprg1 v fb1 i th1 iprg2 plllpf sgnd v in track/ss2 v fb2 i th2 pgood sw2 sense1 + boost1 pgnd bg1 sync/fcb tg1 pgnd tg2 run/ss bg2 n/c pgnd boost2 sense2 + t jmax = 125c, e ja = 90c/w 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 29 25 24 14 23 6 5 4 3 2 1 vfb1 ith1 iprg2 plllpf sgnd v in track/ss2 vfb2 bg1 sync/fcb tg1 pgnd tg2 run/ss n/c bg2 n/c iprg1 sw1 sense1 + boost1 pgnd ith2 pgood sw2 sense2 + boost2 pgnd 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, e ja = 43c/w exposed pad (pin 29) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking package description temperature range LTC3836egn#pbf LTC3836egn#trpbf LTC3836egn 28-lead plastic ssop ?40c to 85c LTC3836eufd#pbf LTC3836eufd#trpbf 3836 28-lead (4mm 5mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics
LTC3836 3 3836fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3836 is guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C40c to 85c operating range are assured by design, characterization and correlation with statistical process controls. parameter conditions min typ max units undervoltage lockout threshold v in falling v in rising l l 1.95 2.15 2.25 2.45 2.55 2.75 v v shutdown threshold at run/ss 0.45 0.65 0.85 v start-up current source run/ss = 0v 0.4 0.65 1 a regulated feedback voltage C40c to 85c (note 5) l 0.591 0.6 0.609 v output voltage line regulation 2.75v < v in < 4.5v (note 5) 0.05 0.2 mv/v output voltage load regulation i th = 0.9v (note 5) i th = 1.7v 0.12 C0.12 0.5 C0.5 % % v fb1,2 input current (note 5) 10 50 na track/ss2 input current track/ss2 = 0v 1 1.5 2.2 a overvoltage protect threshold measured at v fb 0.66 0.68 0.7 v overvoltage protect hysteresis 20 mv auxiliary feedback threshold sync/fcb ramping positive 0.525 0.6 0.675 v top gate (tg) drive 1, 2 rise time c l = 3000pf 40 ns top gate (tg) drive 1, 2 fall time c l = 3000pf 40 ns bottom gate (bg) drive 1, 2 rise time c l = 3000pf 50 ns bottom gate (bg) drive 1, 2 fall time c l = 3000pf 40 ns maximum current sense voltage ( v sense(max) ) (sense + C sw) iprg = floating iprg = 0v iprg = v in l l l 110 70 185 122 82 202 135 95 220 mv mv mv maximum duty cycle in dropout 97 % soft-start time time for v fb1 to ramp from 0.05v to 0.55v 0.6 0.8 1 ms oscillator and phase-locked loop oscillator frequency unsynchronized (sync/fcb not clocked) plllpf = floating plllpf = 0v plllpf = v in 480 260 650 550 300 750 600 340 825 khz khz khz phase-locked loop lock range sync/fcb clocked minimum synchronizable frequency maximum synchronizable frequency l l 850 200 1150 250 khz khz phase detector output current sinking sourcing f osc > f sync/fcb f osc > f sync/fcb C4 4 a a pgood output pgood voltage low i pgood sinking 1ma 140 mv pgood trip level v fb with respect to set output voltage v fb < 0.6v, ramping positive v fb < 0.6v, ramping negative v fb > 0.6v, ramping negative v fb > 0.6v, ramping positive C13 C16 7 10 C10.0 C13.3 10.0 13.3 C7 C10 13 16 % % % % electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise speci? ed. note 3: t j is calculated from the ambient temperature t a and power dissi- pation p d according to the following formula: t j = t a + (p d ? ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the LTC3836 is tested in a feedback loop that servos i th to a speci? ed voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in figure 1.
LTC3836 4 3836fa v sw 2v/div v out 20mv/div ac coupled 2 s/div v in = 3.6v v out = 1.8v i load = 300ma circuit of figure 15 3836 g04 inductor current 5a/div v out ac coupled 100mv/div v in = 3.6v v out = 1.8v continuous mode: 400ma to 4a circuit of figure 15 100 s/div 3836 g02 inductor current 5a/div v out ac coupled 100mv/div v in = 3.6v v out = 1.8v pulse-skipping mode: 400ma to 4a circuit of figure 15 100 s/div 3836 g03 inductor current 5a/div v sw 2v/div v out 20mv/div ac coupled 2 s/div 3836 g05 inductor current 5a/div v in = 3.6v v out = 1.8v i load = 300ma circuit of figure 15 v in = 3.6v r load1 = r load2 = 1 circuit of figure 15 250 s/div 3836 g06 500mv/div v out1 1.8v v out2 1.2v v in = 3.6v r load1 = r load2 = 1 circuit of figure 15 2.50ms/div 3836 g07 500mv/div v out1 1.8v v out2 1.2v input voltage (v) 2.5 C5 normalized frequency shift (%) C4 C2 C1 0 5 2 3.5 3836 g08 C3 3 4 1 3.0 4.0 4.5 sequential start-up typical performance characteristics ef? ciency vs load current load step (forced continuous mode) load step (pulse-skipping mode) light load (pulse-skipping mode) light load (forced continuous mode) tracking start-up with internal soft-start (c run/ss = 0f) tracking start-up with external soft-start (c run/ss = 0.01f) oscillator frequency vs input voltage t a = 25c unless otherwise noted. load current (ma) 30 efficiency (%) 90 100 20 80 50 70 60 40 1 100 1000 10000 3836 g01 10 pulse-skipping mode forced continuous mode sync/fcb = v in sync/fcb = 0v v in = 3.3v v out = 1.5v circuit of figure 15 v in = 3.3v r load1 = r load2 = 1 v out1 : internal soft-start v out2 : c track/ss = 0.047 f circuit of figure 15 4ms/div 3836 g10 500mv/div v out1 1.8v v out2 1.2v
LTC3836 5 3836fa input voltage (v) 2.5 run/ss pin pull-up current ( a) 0.5 0.6 0.7 4.5 3836 g18 0.4 0.3 0 0.1 3.5 3.0 4.0 0.2 0.9 0.8 run/ss = 0v i th voltage (v) 0.5 C20 current limit (%) 0 20 40 60 100 1 1.5 3836 g09 2 80 forced continuous mode pulse-skipping mode typical performance characteristics maximum current sense voltage vs i th pin voltage regulated feedback voltage vs temperature shutdown (run/ss) threshold vs temperature run/ss pull-up current vs temperature maximum current sense threshold vs temperature oscillator frequency vs temperature undervoltage lockout threshold vs temperature t a = 25c unless otherwise noted. shutdown quiescent current vs input voltage run/ss start-up current vs input voltage temperature ( c) C60 115 maximum current sense threshold (mv) 120 125 130 135 C40 C20 0 20 3836 g14 40 60 80 100 i prg = float temperature ( c) C60 feedback voltage (v) 0.600 0.603 0.604 100 3836 g11 0.599 0.598 0.594 C20 20 60 C40 0 40 80 0.596 0.606 0.605 0.602 0.601 0.597 0.595 temperature ( c) C60 0 run/ss voltage (v) 0.1 0.3 0.4 0.5 1.0 0.7 C20 20 40 3836 g12 0.2 0.8 0.9 0.6 C40 0 60 80 100 temperature ( c) C60 0.4 run/ss pull-up current ( a) 0.5 0.6 0.7 0.8 C20 20 60 100 3836 g13 0.9 1.0 C40 0 40 80 temperature ( c) C60 C10 nromalized frequency (%) C8 C4 C2 0 10 4 C20 20 40 3836 g15 C6 6 8 2 C40 0 60 80 100 temperature ( c) C60 input (v in ) voltage (v) 2.30 2.40 100 3836 g16 2.20 2.10 C20 20 60 C40 0 40 80 2.50 2.25 2.35 2.15 2.45 v in rising v in falling input voltage (v) 2.5 0 2 shutdown current ( a) 4 6 8 12 4.5 3836 g17 16 10 14 18 3.5 3.0 4.0
LTC3836 6 3836fa pin functions sw1/sw2 (pins 1, 14)/(pins 26, 11): switch node connection to inductor and external mosfets. also the negative input to differential peak current comparator and an input to the reverse current comparator. normally connected to the source of the main mosfet, the drain of the synchronous mosfet, and the inductor. nc (pins 2, 18)/(pins 16, 28): no connection. iprg1/iprg2 (pins 3, 6)/(pins 27, 3): three-state pins to select maximum peak sense voltage threshold. these pins select the maximum allowed voltage drop between the sense + and sw pins (i.e., the maximum allowed drop across the external main mosfet) for each channel. tie to v in , gnd or ? oat to select 202mv, 82mv, or 122mv respectively. v fb1 /v fb2 (pins 4, 11)/(pins 1, 8): feedback pins. receives the remotely sensed feedback voltage for its con- troller from an external resistor divider across the output. i th1 /i th2 (pins 5, 12)/(pins 2, 9): current threshold and error ampli? er compensation point. nominal operat- ing range on these pins is from 0.7v to 2v. the voltage on these pins determines the threshold of the main current comparator. plllpf (pin 7)/(pin 4): frequency set/pll lowpass filter. when synchronizing to an external clock, this pin serves as the lowpass ? lter point for the phase-locked loop. normally a series rc is connected between this pin and ground. when not synchronizing to an external clock, this pin serves as the frequency select input. tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz operation. floating this pin selects 550khz operation. sgnd (pin 8)/(pin 5): small-signal ground. this pin serves as the ground connection for most internal circuits. v in (pin 9)/(pin 6): small-signal power supply. this pin powers the entire chip except for the gate drivers. externally ? ltering this pin with a lowpass rc network (e.g., r = 10 , c = 1f) is suggested to minimize noise pickup, especially in high load current applications. track/ss2 (pin 10)/(pin 7): channel 2 tracking and soft- start input. the LTC3836 regulates the v fb2 voltage to the (gn package)/(ufd package) smaller of 0.6v or the voltage on the track/ss2 pin. an internal 1.5a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to ? nal regulated output voltage. alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3836 output to track the other supply dur- ing start-up. pgood (pin 13)/(pin 10): power-good output voltage monitor open-drain logic output. this pin is pulled to ground when the voltage on either feedback pin (v fb1 , v fb2 ) is not within 13.3% of its nominal set point. pgnd (pins 17, 22, 26)/(pins 14, 19, 23): power ground. these pins serve as the ground connection for the gate drivers and the negative input to the reverse current comparators. the exposed pad must be soldered to pcb ground. run/ss (pin 20)/(pin 17): run control input and op- tional external soft-start input. forcing this pin below 0.65v shuts down the chip (both channels). driving this pin to v in or releasing this pin enables the chip, using the chips internal soft-start. an external soft-start can be programmed by connecting a capacitor between this pin and ground. tg1/tg2 (pins 23, 21)/(pins 20, 18): top gate drive output. these pins drive the gates of the external topside mosfets. these pins have an output swing from pgnd to boost. sync/fcb (pin 24)/(pin 21): this pin performs two functions: 1) external clock synchronization input for phase-locked loop, and 2) pulse-skipping operation or forced continuous mode select. to synchronize with an external clock using the pll, apply a cmos compatible clock with a frequency between 250khz and 850khz. to select pulse-skipping operation at light loads, tie this pin to v in . grounding this pin selects forced continuous operation, which allows the inductor current to reverse. when synchronized to an external clock, pulse-skipping operation is enabled at light loads. bg1/bg2 (pins 25, 19)/(pins 22, 15): bottom gate drive output. these pins drive the gates of the external synchronous mosfets. these pins have an output swing from pgnd to boost.
LTC3836 7 3836fa functional diagram pin functions (gn/ufd package) boost1/boost2 (pins 27, 16)/(pins 24, 13): positive supply pin for the gate driver circuitry. a bootstrapped capacitor, charged with an external schottky diode and a boost voltage source, is connected between the boost and sw pins. voltage swing at the boost pins is from boost source voltage (typically v in ) to this boost source voltage + v in . sense1 + /sense2 + (pins 28, 5)/(pins 25, 12): positive input to differential current comparator. also powers the gate drivers. normally connected to the drain of the main external mosfet. exposed pad (pin 29) ufd package only: must be sol- dered to pcb ground. (common circuitry) C + C + C + C + shdn 0.6v v ref extss 0.65 a clk1 clk2 fcb 0.54v v fb1 v fb2 fcb 0.6v slope1 slope2 run/ss v in c vin v in (to controller 1, 2) r vin sync/fcb plllpf undervoltage lockout sync detect voltage controlled oscillator slope comp voltage reference t sec = 1ms intss phase detector pgood shdn ov1 uv1 uv2 ov2 37362 fd
LTC3836 8 3836fa functional diagram (controller 1) q ov1 clk1 sc1 fcb slope1 sw1 sense1 + irev1 s r rs1 antishoot through pgnd tg1 sense1 + boost1 v in v out1 c in c out1 bg1 r1b l1 pgnd v fb1 i th1 r ith1 c ith1 0.6v 0.12v sc1 v fb1 sw1 boost1 r1a C + extss intss eamp shdn C + iprg1 C + icmp C + v fb1 ov1 0.68v + C pgnd irev1 iprog1 fcb sw1 3836 fd2 C + switching logic and blanking circuit scp ricmp ovp cb
LTC3836 9 3836fa functional diagram (controller 2) q ov2 clk2 sc2 fcb slope2 sw2 sense2 + shdn irev2 s r rs2 antishoot through pgnd boost2 tg2 sense2 + v in v out2 c out2 bg2 r2b r trackb r tracka l2 pgnd v fb2 i th2 track/ss2 r ith2 c ith2 shdn 1 a 0.12v sc2 track v fb2 sw2 r2a v out1 eamp C + C + icmp C + v fb2 ov2 0.68v + C pgnd irev2 fcb sw2 3836 fd3 C + switching logic and blanking circuit ovp scp iprg2 boost2 c in cb 0.60v C +
LTC3836 10 3836fa operation (refer to functional diagram) main control loop the LTC3836 uses a constant-frequency, current mode architecture with the two controllers operating 180 degrees out-of-phase. during normal operation, the top external power mosfet is turned on when the clock for its chan- nel sets the rs latch, and turned off when the current comparator (i cmp ) resets the latch. the peak inductor current at which i cmp resets the rs latch is determined by the voltage on the i th pin, which is driven by the output of the error ampli? er (eamp). the v fb pin receives the output voltage feedback signal from an external resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp . when the load current increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top n-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator, i rcmp , or the beginning of the next cycle. shutdown, soft-start and tracking start-up (run/ss and track/ss2 pins) the LTC3836 is shut down by pulling the run/ss pin low. in shutdown, all controller functions are disabled and the chip draws only 6.5a. the tg and bg outputs are held low (off) in shutdown. releasing run/ss allows an internal 0.65a current source to charge up the run/ss pin. when the run/ss pin reaches 0.65v, the LTC3836s two controllers are enabled. the start-up of v out1 is controlled by the LTC3836s internal soft-start. during soft-start, the error ampli? er eamp compares the feedback signal v fb1 to the internal soft-start ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its ? nal value, while maintaining control of the inductor current. the 1ms soft-start time can be increased by con- necting the optional external soft-start capacitor c ss between the run/ss and sgnd pins. as the run/ss pin continues to rise linearly from approximately 0.65v to 1.3v (being charged by the internal 0.65a current source), the eamp regulates the v fb1 proportionally from 0v to 0.6v. the start-up of v out2 is controlled by the voltage on the track/ss2 pin. when the voltage on the track/ss2 pin is less than the 0.6v internal reference, the LTC3836 regulates the v fb2 voltage to the track/ss2 pin voltage instead of the 0.6v reference. this allows the track/ss2 pin to be used to program a soft-start by connecting an external capacitor from the track/ss2 pin to sgnd. an internal 1a pull-up current charges this capacitor, creating a voltage ramp on the track/ss2 pin. as the track/ss2 voltage rises linearly from 0v to 0.6v (and beyond), the output voltage v out2 rises smoothly from zero to its ? nal value. alternatively, the track/ss2 pin can be used to cause the start-up of v out2 to track that of another supply. typi- cally, this requires connecting to the track/ss2 pin an external resistor divider from the other supply to ground (see applications information section). when the run/ss pin is pulled low to disable the LTC3836, or when v in drops below its undervoltage lockout threshold, the track/ss2 pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off. light load operation (pulse-skipping or continuous conduction) (sync/fcb pin) the LTC3836 can be enabled to enter high ef? ciency pulse- skipping operation or forced continuous conduction mode at low load currents. to select pulse-skipping operation, tie the sync/fcb pin to a dc voltage above 0.6v (e.g., v in ). to select forced continuous operation, tie the sync/fcb to a dc voltage below 0.6v (e.g., sgnd). in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. the main n-channel mosfet is turned on every cycle (constant-frequency) regardless of the i th pin voltage. in this mode, the ef? ciency at light loads is lower than in pulse-skipping operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry.
LTC3836 11 3836fa operation (refer to functional diagram) when the sync/fcb pin is tied to a dc voltage above 0.6v or when it is clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop), the LTC3836 operates in pwm pulse-skipping mode at light loads. in this mode, the current comparator i cmp may remain tripped for several cycles and force the main n-channel mosfet to stay off for the same number of cycles. the inductor current is not allowed to reverse, though (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference. however, it provides low current ef? ciency higher than forced continuous mode. during start-up or a short-circuit condition (v fb1 or v fb2 0.54v), the LTC3836 operates in pulse-skipping mode (no cur- rent reversal allowed), regardless of the state of the sync/fcb pin. short-circuit protection when an output is shorted to ground (v fb < 0.12v), the switching frequency of that controller is reduced to one- ? fth of the normal operating frequency. the other controller maintains regulation in pulse-skipping mode. the short-circuit threshold on v fb2 is based on the smaller of 0.12v and a fraction of the voltage on the track/ss2 pin. this also allows v out2 to start up and track v out1 more easily. note that if v out1 is truly short-circuited (v out1 = v fb1 = 0v), then the LTC3836 will try to regulate v out2 to 0v if a resistor divider on v out1 is connected to the track/ss pin. output overvoltage protection as a further protection, the overvoltage comparator (ov) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the main n-channel mosfet is turned off and the synchronous n-channel mosfet is turned on until the overvoltage is cleared. frequency selection and phase-locked loop (plllpf and sync/fcb pins) the selection of switching frequency is a tradeoff between ef? ciency and component size. low frequency opera- tion increases ef? ciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the LTC3836s controllers can be selected using the plllpf pin. if the sync/fcb is not being driven by an external clock source, the plllpf can be ? oated, tied to v in or tied to sgnd to select 550khz, 750khz or 300khz respectively. a phase-locked loop (pll) is available on the LTC3836 to synchronize the internal oscillator to an external clock source that is connected to the sync/fcb pin. in this case, a series rc should be connected between the plllpf pin and sgnd to serve as the plls loop ? lter. the LTC3836 phase detector adjusts the voltage on the plllpf pin to align the turn-on of controller 1s top mosfet to the ris- ing edge of the synchronizing signal. thus, the turn-on of controller 2s top mosfet is 180 degrees out-of-phase with the rising edge of the external clock source. the typical capture range of the LTC3836s phase-locked loop is from approximately 200khz to 1mhz, and is guar- anteed over temperature between 250khz and 850khz. in other words, the LTC3836s pll is guaranteed to lock to an external clock source whose frequency is between 250khz and 850khz. dropout operation each top mosfet driver is biased from the ? oating boot- strap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detec- tor detects this and forces the top mosfet off for about 200ns every fourth cycle to allow c b to recharge.
LTC3836 12 3836fa operation (refer to functional diagram) undervoltage lockout to prevent operation of the external mosfets below safe input voltage levels, an undervoltage lockout is incorpo- rated in the LTC3836. when the input supply voltage (v in ) drops below 2.25v, the external mosfets and all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes. peak current sense voltage selection and slope compensation (iprg1 and iprg2 pins) when a controller is operating below 20% duty cycle, the peak current sense voltage (between the sense + and sw pins) allowed across the main n-channel mosfet is determined by: v sense(max) = av ith ? 0.7v () 10 where a is a constant determined by the state of the iprg pins. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to sgnd selects a = 2/3. the maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the main n-channel mosfet is 122mv, 202mv, or 82mv for the three respective states of the iprg pin. the peak sense voltages for the two controllers can be independently selected by the iprg1 and iprg2 pins. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in figure 1. the peak inductor current is determined by the peak sense voltage and the on-resistance of the main n-chan- nel mosfet: i pk = v sense(max) r ds(on ) power-good (pgood) pin a window comparator monitors both feedback voltages and the open-drain pgood output pin is pulled low when either or both feedback voltages are not within 10% of the 0.6v reference voltage. pgood is low when the LTC3836 is shut down or in undervoltage lockout. 2-phase operation why the need for 2-phase operation? many constant-fre- quency dual switching regulators operate both controllers in phase (i.e., single phase operation). this means that both topside mosfets are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. these large amplitude pulses increase the total rms current ? owing in the input capacitor, requiring the use of larger and more expensive input capacitors, and increase both emi and power losses in the input capacitor and input power supply. with 2-phase operation, the two controllers of the LTC3836 are operated 180 degrees out-of-phase. this effectively interleaves the current pulses coming from the topside mosfet switches, greatly reducing the time where they overlap and add together. the result is a signi? cant reduc- tion in the total rms current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for emi and improves real world operating ef? ciency. duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 37362 f01 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 figure 1. maximum peak current vs duty cycle
LTC3836 13 3836fa operation (refer to functional diagram) figure 2 shows example waveforms for a single phase dual controller versus a 2-phase LTC3836 system. in this case, two outputs of different voltage, each drawing the same load current are derived from a single input supply. in this example, 2-phase operation could halve the rms input capacitor current. while this is an impressive reduction by itself, remember that power losses are proportional to i rms 2 , meaning that just one-fourth the actual power is wasted. the reduced input ripple current also means that less power is lost in the input power path, which could include batter- ies, switches, trace/connector resistances, and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. signi? cant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower rms current-rated input capacitors. of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two control- lers, which in turn are dependent upon the input supply voltage. figure 3 depicts how the rms input current varies for single phase and 2-phase dual controllers with 2.5v and 1.8v outputs. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. single phase dual controller 2-phase dual controller sw1 (v) sw2 (v) i l1 i l2 i in 3836 f02 input voltage (v) 0 input capacitor rms current 0.2 0.6 0.8 1.0 2.0 1.4 3.0 4.0 4.5 3836 f03 0.4 1.6 1.8 1.2 3.5 single phase dual controller 2-phase dual controller v out1 = 2.5v/2a v out2 = 1.8v/2a figure 2. example waveforms for a single phase dual controller vs the 2-phase LTC3836 figure 3. rms input current comparison
LTC3836 14 3836fa applications information the typical LTC3836 application circuit is shown in figure 13. external component selection for each of the LTC3836s controllers is driven by the load requirement and begins with the selection of the inductor (l) and the power mosfets (m1 to m4). power mosfet selection each of the LTC3836s two controllers requires two ex- ternal n-channel power mosfets for the topside (main) switch and the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss , turn-off delay t d(off) and the total gate charge q g . the gate drive voltage is the input supply voltage. since the LTC3836 is designed for operation down to low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. the main mosfets on-resistance is chosen based on the required load current. the maximum average output load current i out(max) is equal to the peak inductor current minus half the peak-to-peak ripple current i ripple . the LTC3836s current comparator monitors the drain-to- source voltage v ds of the main mosfet, which is sensed between the sense + and sw pins. the peak inductor cur- rent is limited by the current threshold, set by the voltage on the i th pin of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold v sense(max) to approximately 122mv when iprg is ? oating (82mv when iprg is tied low; 202mv when iprg is tied high). the output current that the LTC3836 can provide is given by: i out(max) = v sense(max) r ds(on ) ? i ripple 2 a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r ds(on)(max) = 5 6 ? v sense(max) i out(max ) for duty cycle < 20%. however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: r ds(on)(max) = 5 6 ?sf? v sense(max) i out ( max ) where sf is a scale factor whose value is obtained from the curve in figure 1. these must be further derated to take into account the signi? cant variation in on-resistance with temperature. the following equation is a good guide for determining the required r ds(on)max at 25c (manufacturers speci? ca- tion), allowing some margin for variations in the LTC3836 and external component values: r ds(on)(max) = 5 6 ? 0.9 ? sf ? v sense(max) i out(max) ? t the t is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/c, as shown in figure 4. junction to case temperature t jc is about 10c in most applications. for a maximum ambi- ent temperature of 70c, using 80c 1.3 in the above equation is a reasonable choice. the power dissipated in the top and bottom mosfets strongly depends on their respective duty cycles and load current. when the LTC3836 is operating in continuous mode, the duty cycles for the mosfets are: top mosfet duty cycle = v out v i n bottom mosfet duty cycle = v in ?v out v i n
LTC3836 15 3836fa applications information the mosfet power dissipations at maximum output current are: p top = v out v i n ?i out(max) 2 ? t ?r ds(on) + 2?v in 2 ?i out(max) ?c rss ?f osc p bot = v in ?v out v i n ?i out(max) 2 ? t ?r ds(on) both mosfets have i 2 r losses and the p top equation includes an additional term for transition losses, which are largest at high input voltages. the bottom mosfet losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is nearly 100%. the LTC3836 utilizes a nonoverlapping, antishoot-through gate drive control scheme to ensure that the mosfets are not turned on at the same time. to function properly, the control scheme requires that the mosfets used are intended for dc/dc switching applications. many power mosfets are intended to be used as static switches and therefore are slow to turn on or off. operating frequency and synchronization the choice of operating frequency, f osc , is a trade-off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation requires more inductance for a given amount of ripple current. the internal oscillator for each of the LTC3836s controllers runs at a nominal 550khz frequency when the plllpf pin is left ? oating and the sync/fcb pin is a dc low or high. pulling the plllpf to v in selects 750khz operation; pulling the plllpf to gnd selects 300khz operation. alternatively, the LTC3836 will phase-lock to a clock signal applied to the sync/fcb pin with a frequency between 250khz and 850khz (see phase-locked loop and fre- quency synchronization). inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i ripple = v out v i n v in ?v out f osc ? l lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest ef? ciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a speci? ed maximum, the inductor should be chosen according to: l v in ?v out f osc ?i rippl e ? v out v i n junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 3836 f04 0.5 0 0 50 100 2.0 figure 4. r ds(on) vs temperature
LTC3836 16 3836fa applications information inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a ? xed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! schottky diode selection (optional) the schottky diodes d1 and d2 in figure 16 conduct current during the dead time between the conduction of the power mosfets . this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in ef? ciency. a 1a schottky diode is generally a good size for most LTC3836 applications, since it conducts a relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. this diode may be omitted if the ef? ciency loss can be tolerated. c in and c out selection the selection of c in is simpli? ed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the main n-chan- nel mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v i n v out () v in ?v out () 1/ 2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3836, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the bene? t of the LTC3836 2-phase operation can be cal- culated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both control- lers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall bene? t of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the ef? ciency testing. the drains of the main mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in .
LTC3836 17 3836fa applications information a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3836, is also suggested. a 10 resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is approximated by: v out i ripple esr + 1 8fc ou t where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the LTC3836 output voltages are each set by an external feedback resistor divider carefully placed across the out- put, as shown in figure 5. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. run/soft-start function the run/ss pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the LTC3836. pulling the run/ss pin below 0.65v puts the LTC3836 into a low quiescent current shutdown mode (i q = 6.5a). if run/ss has been pulled all the way to ground, there will be a delay before the LTC3836 comes out of shutdown and is given by: t delay = 0.65v ? c ss 0.65 a = 1s / f?c ss this pin can be driven directly from logic as shown in figure 6. diode d ss in figure 6 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. this diode (and capacitor) can be deleted if the external soft-start is not needed. 1/2 LTC3836 v fb v out r b c ff r a 3836 f05 3.3v or 5v run/ss run/ss c ss c ss (internal soft-start) d ss 3836 f06 v dd v in run/ss figure 5. setting output voltage figure 6. run/ss pin interfacing
LTC3836 18 3836fa applications information during soft-start, the start-up of v out1 is controlled by slowly ramping the positive reference to the error ampli? er from 0v to 0.6v, allowing v out1 to rise smoothly from 0v to its ? nal value. the default internal soft-start time is 1ms. this can be increased by placing a capacitor between the run/ss pin and sgnd. in this case, the soft-start time will be approximately: t ss1 = c ss ? 600mv 0.65 a tracking the start-up of v out2 is controlled by the voltage on the track/ss2 pin. normally this pin is used to allow the start- up of v out2 to track that of v out1 as shown qualitatively in figures 7a and 7b. when the voltage on the track/ss2 pin is less than the internal 0.6v reference, the LTC3836 regulates the v fb2 voltage to the track/ss2 pin voltage instead of 0.6v. the start-up of v out2 may ratiometrically track that of v out1 , according to a ratio set by a resistor divider (figure 7c): v out1 v out 2 = r2a r track a ? r tracka + r trackb r2b + r2 a for coincident tracking (v out1 = v out2 during start-up), r2a = r tracka r2b = r trackb the ramp time for v out2 to rise from 0v to its ? nal value is: t ss2 = t ss1 ? 0.6 v out1 f ? r tracka + r trackb r track a LTC3836 v fb2 v out2 v out1 v fb1 track/ss2 r2b r2a 3836 f07a r1b r1a r tracka r trackb time (7b) coincident tracking v out1 v out2 output voltage time 3836 f07b_c (7c) ratiometric tracking v out1 v out2 output voltage figure 7a. using the track/ss pin figures 7b and 7c. two different modes of output voltage tracking
LTC3836 19 3836fa applications information for coincident tracking, t ss2 = t ss1 ? v out2f v out1 f where v out1f and v out2f are the ? nal, regulated values of v out1 and v out2 . v out1 should always be greater than v out2 when using the track/ss2 pin for tracking. if no tracking function is desired, then the track/ss2 pin may be tied to a capacitor to ground, which sets the ramp time to ? nal regulated output voltage. phase-locked loop and frequency synchronization the LTC3836 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the main n-channel mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the sync/fcb pin. the turn-on of controller 2s main n-channel mosfet is thus 180 degrees out-of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the external ? lter network connected to the plllpf pin. the relationship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/ fcb, is shown in figure 8 and speci? ed in the electrical characteristics table. note that the LTC3836 can only be synchronized to an external clock whose frequency is within range of the LTC3836s internal vco, which is nominally 200khz to 1mhz. this is guaranteed, over temperature and variations, to be between 300khz and 750khz. a simpli? ed block diagram is shown in figure 9. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the plllpf pin. if the external and internal frequencies plllpf pin voltage (v) 0 0 frequency (khz) 0.5 1 1.5 2 3836 f08 2.4 200 400 600 800 1000 1200 1400 figure 8. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock figure 9. phase-locked loop block diagram digital phase/ frequency detector oscillator 2.4v r lp c lp 3836 f09 plllpf external oscillator sync/ fcb
LTC3836 20 3836fa applications information are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the ? lter capacitor c lp holds the voltage. the loop ? lter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the ? lter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01f. typically, the external clock (on sync/fcb pin) input high level is 1.6v, while the input low level is 1.2v. table 1 summarizes the different states in which the plllpf pin can be used. table 1. plllpf pin sync/fcb pin frequency 0v dc voltage 300khz floating dc voltage 550khz v in dc voltage 750khz rc loop filter clock signal phase-locked to external clock 5v supply is available. note that in applications where the supply voltage to c b exceeds v in , the boost pin will draw approximately 500a in shutdown mode. table 2 summarizes the different states in which the sync/fcb pin can be used table 2. sync/fcb pin condition 0v to 0.5v forced continuous mode current reversal allowed 0.7v to v in pulse-skipping operation enabled no current reversal allowed external clock signal enable phase-locked loop (synchronize to external clk) pulse-skipping at light loads no current reversal allowed figure 11. foldback current limiting topside mosfet drive supply (c b , d b ) in the functional diagram, external bootstrap capaci- tor c b is charged from a boost power source (usually v in ) through diode d b when the sw node is low. when a mosfet is to be turned on, the c b voltage is applied across the gate-source of the desired device. when the topside mosfet is on, the boost pin voltage is above the input supply. v boost = 2v in . c b must be 100 times the total input capacitance of the topside mosfet. the reverse breakdown of d b must be greater than v in(max) . figure 6 shows how a 5v gate drive can be achieved if a secondary fault condition: short-circuit and current limit to prevent excessive heating of the bottom mosfet, foldback current limiting can be added to reduce the cur- rent in proportion to the severity of the fault. foldback current limiting is implemented by adding diodes d fb1 and d fb2 between the output and the i th pin as shown in figure 11. in a hard short (v out = 0v), the current will be reduced to approximately 50% of the maximum output current. + 1/2 LTC3836 v fb i th r2 d fb1 v out d fb2 3836 f11 r1
LTC3836 21 3836fa applications information using a sense resistor a sense resistor r sense can be connected between v in and sw to sense the output load current. in this case, the drain of the topside n-channel mosfet is connected to sense C pin and the source is connected to the sw pin of the LTC3836. therefore, the current comparator monitors the voltage developed across r sense , not the v ds of the top mosfet. the output current that the LTC3836 can provide in this case is given by: i out(max) = v sense(max) r ds(on ) ? i ripple 2 setting ripple current as 40% of i out(max) and using figure 1 to choose sf, the value of r sense is: r sense = 5 6 ?sf? v sense(max) i out(max ) variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of an external mosfet. therefore the load current is well controlled with a sense resistor. however the sense resistor causes extra i 2 r losses in addition to those of the mosfet. therefore, using a sense resistor lowers the ef? ciency of LTC3836, especially at high load currents. low supply operation although the LTC3836 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 12 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the LTC3836 is capable of turning the main n-chan- nel mosfet on and then off. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle and high frequency applica- tions may approach the minimum on-time limit and care should be taken to ensure that: t on(min) < v out f osc ?v i n if the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3836 will begin to skip cycles (unless forced continuous mode is selected). the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on- time for the LTC3836 is typically about 200ns. however, as the peak sense voltage (i l(peak) ? r ds(on) ) decreases, the minimum on-time gradually increases up to about 250ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if forced continuous mode is selected and the duty cycle falls below the minimum on-time requirement, the output will be regulated by overvoltage protection. figure 12. line regulation of v ref and maximum sense voltage for low input supply input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 3836 f12 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage
LTC3836 22 3836fa applications information ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, ? ve main sources usually account for most of the losses in LTC3836 circuits: 1) LTC3836 dc bias cur- rent, 2) mosfet gate charge current, 3) i 2 r losses, and 4) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, excluding mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from sense + to ground. the resulting dq/dt is a current out of sense + , which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfets and inductor. in continuous mode, the average output current ? ows through l but is chopped between the top mosfet and the bottom mosfet. the mosfet r ds(on) s multiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) transition losses apply to the top mosfet and increase with higher operating frequencies and input voltages. transition losses can be estimated from: transition loss = 2 (v in ) 2 i o(max) c rss (f) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( i load )(esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then returns v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c ? lter (see functional diagram) sets the dominant pole-zero loop compensation. the i th external components shown in the typical application on the front page of this data sheet will provide an adequate starting point for most applications. the values can be modi? ed slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increasing r c , and the bandwidth of the loop will be increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimiz- ing the compensation components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. opti-loop is a trademark of linear technology corporation.
LTC3836 23 3836fa applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3836. these items are illustrated in the layout diagram of figure 13. figure 14 depicts the current waveforms present in the various branches of the 2-phase dual regulator. 1) the power loop (input capacitor, mosfets, inductor, output capacitor) of each channel should be as small as possible and isolated as much as possible from the power loop of the other channel. ideally, the main and synchronous fets should be connected close to one another with an input capacitor placed right at the fets. it is better to have two separate, smaller valued input capacitors (e.g., two 10f one for each channel) than it is to have a single larger valued capacitor (e.g., 22f) that the channels share with a common connection. 2) the signal and power grounds should be kept separate. the signal ground consists of the feedback resistor divid- ers, i th compensation networks and the sgnd pin. the power grounds consist of the (C) terminal of the input and output capacitors and the source of the synchronous n-channel mosfet. each channel should have its own power ground for its power loop (as de- scribed above in item 1). the power grounds for the two channels should connect together at a common point. it is most important to keep the ground paths with high switching currents away from each other. the pgnd pins on the LTC3836 should be shorted together and connected to the common power ground connection (away from the switching currents). 3) put the feedback resistors close to the v fb pins. the trace connecting the top feedback resistor (r b ) to the output capacitor should be a kelvin trace. the i th compensation components should also be very close to the LTC3836. 4) the current sense traces (sense + and sw) should be kelvin connections right at the main n-channel mosfet drains and sources. 5) keep the switch nodes (sw1, sw2) and the gate driver nodes (tg1, tg2, bg1, bg2) away from the small- signal components, especially the opposite channels feedback resistors, i th compensation components, and the current sense pins (sense + and sw). 6) connect the boost capacitors to the switch nodes, not to the small signal nodes swn. connect the boost diodes to the positive terminal of the input capacitor. figure 13. LTC3836 layout diagram n/c iprg1 v fb1 i th1 iprg2 plllpf sgnd v in track/ss2 v fb2 i th2 pgood boost1 sync/fcb bg1 pgnd 27 24 25 26 pgnd tg2 bg2 run/ss 22 21 19 20 sense1 + n/c pgnd boost2 sense2 + sw2 tg1 sw1 1 3 4 5 6 7 8 9 10 11 12 13 2 28 18 17 16 15 14 23 LTC3836egn + + c out1 c out2 c vin1 c vin v out1 v out2 bold lines indicate high current paths 3836 f13 l1 l2 m1 m2 m3 m4 v in c vin2 d b2 d b1 c b2 c b1
LTC3836 24 3836fa applications information figure 14. branch current waveforms figure 15. 2-phase, 550khz, dual output synchronous dc/dc converter with ceramic output capacitors r l1 l1 v out1 c out1 + v in c in r in + r l2 bold lines indicate high, switching current lines. keep lines to a minimum length l2 3836 f14 v out2 c out2 + l1, l2: vishay ihlp2525czerr 47m01 c in : 22 f x2, 6.3v, x5r c out1 , c out2 : taiyo yuden jmk235bj107mm x2 m1-m4: vishay si7882dp c ith2a , 82pf r ith1 , 15.8k c ith1 , 820pf c ith1a , 82pf d b1 r fb1a , 59k l1 l2 sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 boost1 boost2 v in pgood v fb2 n/c n/c 16 28 track/ss2 i th2 tg2 LTC3836eufd pgnd tg1 sync/fcb bg1 pgnd pgnd sense1 + run/ss bg2 pgnd sw2 sense2 + r tracka , 11.8k r plllpf c plllpf c ss , 10nf v in 2.75v to 4.5v v out1 1.8v 15a v out2 1.2v 15a c in x2 c vin , 1 f c ith2 , 820pf c b2 , 0.22 f c out2 x2 c out1 x2 3836 f15 r vin , 10 r fb2a , 59k r ith2 , 15.8k c b1 , 0.22 f d b2 m3 d2 d1 r trackb , 12.4k r fb1b , 118k c ffw1 , 33pf r fb2b , 59k m2 5 4 3 27 1 2 6 10 8 7 9 21 17 26 24 13 18 19 20 22 29 23 25 15 14 11 12 m1 m4
LTC3836 25 3836fa applications information figure 16a. 2-phase, 750khz, dual output synchronous dc/dc converter figure 16b. ef? ciency vs load current figure 16c. load step load current (ma) 30 efficiency (%) 90 100 20 10 0 80 50 70 60 40 10 1000 10000 3836 f16b 100 channel 1 1.5v channel 2 1.1v 40 s/div v out 200mv/div ac coupled i l1 5a/div i l2 5a/div i load 5a/div 3836 f17c v in = 3.3v v out = 1.25v i load = 10a to 15a l1, l2: vishay ihlp2525czerr 47m01 c in : 22 f x2, 6.3v, x5r c out1 , c out2 : sanyo poscap , 2r5tpe330m m1, m2: fairchild fds6898a c ith2a , 47pf r ith1 , 64.9k c ith1 , 470pf c ith1a , 47pf d b1 r fb1a , 59k, 1% l1 l2 sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 boost1 boost2 v in pgood v fb2 n/c n/c 16 28 track/ss2 i th2 tg2 LTC3836eufd pgnd tg1 sync/fcb bg1 pgnd pgnd sense1 + run/ss bg2 pgnd sw2 sense2 + c ss2 , 10nf c ss , 10nf v in 3.3v v out1 1.5v 5a v out2 1.1v 5a c in x2 c vin , 1 f c ith2 , 470pf c b2 , 0.22 f c out2 c out1 3836 f16 r vin , 10 r fb2a , 59k, 1% r ith2 , 64.9k c b1 , 0.22 f d b2 d2 d1 r fb1b , 88.7k, 1% c ffw1 , 82pf r fb2b 49.9k, 1% c ffw2 , 82pf m2 5 4 3 27 1 2 6 10 8 7 9 21 17 26 24 13 18 19 20 22 29 23 25 15 14 11 12 m1 + +
LTC3836 26 3836fa typical applications figure 17a. single output, high current application with external frequency synchronization figure 17b. ef? ciency vs load current figure 17c. load step l1, l2: toko 0.47 f fdv0630-r47m=p3 c in : 22 f x3, 6.3v, x5r c out : avx corecap 560 f, 2.5v npv v567m002 r003 m1, m2, m3, m4: siliconix si7882dp c ith2a , 100pf r ith1 , 1.37k c ith1 , 2700pf c ith1a , 100pf d b1 r fb1a , 61.9k l1 l2 sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 boost1 boost2 v in pgood v fb2 n/c n/c 16 28 track/ss2 i th2 tg2 LTC3836eufd pgnd tg1 sync/fcb bg1 pgnd pgnd sense1 + run/ss bg2 pgnd sw2 sense2 + r tracka , 61.9k r plllpf , 15k c plllpf , 0.015 f c ss , 10nf v in 2.75v to 4.2v 500khz v out 1.25v 20a c in x3 c vin , 10 f c b2 , 0.22 f c out 3836 f17 r vin , 10 c b1 , 0.22 f d b2 m3 d1 b320a d2 b320a r trackb , 68.1k r fb1b , 66.5k c ffw1 , 120pf m2 5 4 3 27 1 2 6 10 8 7 9 21 17 26 24 13 18 19 20 22 29 23 25 15 14 11 12 m1 m4 + load current (ma) 30 efficiency (%) 90 100 20 80 50 70 60 40 10 1000 10000 100000 3836 f17b 100 v in = 4.2v v in = 2.7v v in = 3.6v 40 s/div v out 200mv/div ac coupled i l1 5a/div i l2 5a/div i load 5a/div 3836 f17c v in = 3.3v v out = 1.25v i load = 10a to 15a
LTC3836 27 3836fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712) .386 C .393* (9.804 C 9.982) gn28 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 4.00 0.10 (2 sides) 2.65 0.10 (2 sides) 5.00 0.10 (2 sides) 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom viewexposed pad 3.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0405 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 (2 sides) 3.65 0.05 (2 sides) 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline
LTC3836 28 3836fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0807 rev a ? printed in usa related parts part number description comments ltc1735 high ef? ciency synchronous step-down controller burst mode ? operation, 16-pin narrow ssop , 3.5v v in 36v ltc1778 no r sense tm synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc2923 power supply tracking controller controls up to three supplies, 10-lead msop ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, i q = 60a, i sd = <1a, ms package ltc3412a 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out = 0.8v, i q = 60ma, i sd = <1ma, tssop-16e and 4mm 4mm qfn packages ltc3415 7a, polyphase synchronous step-down regulator with output tracking and margining v in : 2.5v to 5.5v, spread spectrum operation, 5mm 7mm qfn package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter with output tracking 95% ef? ciency, v in : 2.25v to 5.5v, i sd = <1a, tssop-20e package ltc3418 8a, 4mhz synchronous step-down regulator v in : 2.25v to 5.5v, 5mm 7mm qfn package ltc3701 2-phase, low input voltage dual step-down dc/dc controller 2.5v v in 9.8v, 550khz, pgood, pll, 16-lead ssop ltc3708 fast 2-phase, no r sense buck controller with output tracking constant on-time dual controller, v in up to 36v, very low duty cycle operation, 5mm 5mm qfn package ltc3728/ltc3728l dual, 550khz, 2-phase synchronous step-down switching regulator constant-frequency, v in to 36v, 5v and 3.3v ldos, 5mm 5mm qfn or 28-lead ssop ltc3736 dual, 2-phase, no r sense synchronous controller 2.75v v in 9.8v, output tracking, burst mode operation ltc3736-1 dual, 2-phase, no r sense synchronous controller with spread spectrum v in : 2.75v to 9.8v, 4mm 4mm qfn package spread spectrum operation; output tracking ltc3736-2 2-phase, no r sense , dual synchronous controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 0.6v 1% reference, high current limit, 4mm 4mm qfn package ltc3737 dual, 2-phase, no r sense controller with output tracking non-synchronous constant-frequency with pll, 4mm 4mm qfn and 24-lead ssop packages ltc3772 no r sense step-down dc/dc controller 2.75v v in 9.8v, sot-23 or 3mm 2mm dfn packages ltc3776 dual, 2-phase, no r sense synchronous controller for ddr/ qdr memory termination provides v ddq and v tt with one ic, 2.75v v in 9.8v, 4mm 4mm qfn and 24-lead ssop packages ltc3808 no r sense , low emi, synchronous step-down controller with output tracking 2.75v v in 9.8v; spread spectrum operation; 3mm 4mm dfn and 16-lead ssop packages ltc3809/ltc3809-1 no r sense synchronous step-down controllers 2.75v to 9.8v, 3mm 3mm dfn and 10-lead msope packages ltc3822 no r sense , low v in , all n-channel mosfet, synchronous step-down dc/dc controller 2.75v v in 4.5v; 0.6v v out v in , 10-lead ms and 3mm x 3mm dfn packages ltc3822-1 no r sense , low v in , all n-channel mosfet, synchronous step-down dc/dc controller with external soft-start 2.75v v in 4.5v; 0.6v v out v in , 16-lead ssop and 3mm x 3mm dfn packages burst mode is a registered trademark of linear technology corporation.

▲Up To Search▲

Price & Availability of LTC3836

	To Download LTC3836 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .